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Acceleration of Data Compression Algorithms on Sony PS3 Platform
Breitenbacher, Dominik ; Jaroš, Jiří (referee) ; Šimek, Václav (advisor)
This paper presents the use of PlayStation 3 device for accelerating compression algorithms and tries to show the potencial of PlayStation 3 for use on these tasks. For a demonstration was selected compression method based on the Burrows-Wheeler transformation. The output of the transformation is further transformed by using the Move-To-Front transformation and subsequently encoded by the static Huffman encoding. The compression algorithm has been called PS3BWT. It performs compression by using each of tasks and tries to always use the maximum number of avaible processor units, so the compression is carried out as quickly as possible.
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Acceleration of Data Compression Algorithms on Sony PS3 Platform
Breitenbacher, Dominik ; Jaroš, Jiří (referee) ; Šimek, Václav (advisor)
This paper presents the use of PlayStation 3 device for accelerating compression algorithms and tries to show the potencial of PlayStation 3 for use on these tasks. For a demonstration was selected compression method based on the Burrows-Wheeler transformation. The output of the transformation is further transformed by using the Move-To-Front transformation and subsequently encoded by the static Huffman encoding. The compression algorithm has been called PS3BWT. It performs compression by using each of tasks and tries to always use the maximum number of avaible processor units, so the compression is carried out as quickly as possible.
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Implementation of video compression into FPGA chip
Tomko, Jakub ; Fujcik, Lukáš (referee) ; Bohrn, Marek (advisor)
This thesis is focused on the compression algorithm's analysis of MJPEG format and its implementation in FPGA chip. Three additional video bitstream reduction methods have been evaluated for real-time low latency applications of MJPEG format. These methods are noise filtering, inter-frame encoding and lowering video's quality. Based on this analysis, a MJPEG codec has been designed for implementation into FPGA chip XC6SLX45, from Spartan-6 family.
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