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National Repository of Grey Literature 2 records found  Search took 0.02 seconds. 
EUS FS Reference Design
 Jíša, Pavel ; Kváš, Marek (referee) ; Valach, Soběslav (advisor)
This bechelor thesis, in the first part, is focused on a description of the EUS FS device and in a second part there is created reference excercise on gate array FPGA and other examples on cooperation of a gate array and linux processor. Next step describes the BUS programme which is designed for a work with a bus. There has been made a modification of this Bus programme.
Detailed record
EUS FS Reference Design
 Jíša, Pavel ; Kváš, Marek (referee) ; Valach, Soběslav (advisor)
This bechelor thesis, in the first part, is focused on a description of the EUS FS device and in a second part there is created reference excercise on gate array FPGA and other examples on cooperation of a gate array and linux processor. Next step describes the BUS programme which is designed for a work with a bus. There has been made a modification of this Bus programme.
Detailed record

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