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Perfecting the analysis of 10Gbit/s computer network
Ťápal, Tomáš ; Polívka, Michal (referee) ; Škorpil, Vladislav (advisor)
The master’s thesis consists of several parts. Describes the technology 10 Gbps Ethernet. Analyzer Ixia and Endace presents, especially their use for traffic analysis and stress testing the network devices. It deals with documents RFC concerning the routers and switch testing. Thesis includes the reports of tests switches and router performed by RFC 2544 and RFC 2889 documents. Part of the thesis is dedicated to COMBO FPGA cards. Documentations to the analyzers is created in this thesis and macro is on the CD for presentation of measurement results.
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Routing in High-speed Computer Networks
Vlček, Lukáš ; Hanák, Pavel (referee) ; Škorpil, Vladislav (advisor)
Goal of this master thesis is to introduce and bring up basics and principles of NetCOPE framework in many details using "first approach" method for exploration of its internal structures - mainly focusing on application core using VHDL for focus itself. Furthermore, this knowledge is used for design and implementation of filtration system for network traffic with more details within phase of design in VHDL language.
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Perfecting the analysis of 10Gbit/s computer network
Ťápal, Tomáš ; Polívka, Michal (referee) ; Škorpil, Vladislav (advisor)
The master’s thesis consists of several parts. Describes the technology 10 Gbps Ethernet. Analyzer Ixia and Endace presents, especially their use for traffic analysis and stress testing the network devices. It deals with documents RFC concerning the routers and switch testing. Thesis includes the reports of tests switches and router performed by RFC 2544 and RFC 2889 documents. Part of the thesis is dedicated to COMBO FPGA cards. Documentations to the analyzers is created in this thesis and macro is on the CD for presentation of measurement results.
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|
|
Routing in High-speed Computer Networks
Vlček, Lukáš ; Hanák, Pavel (referee) ; Škorpil, Vladislav (advisor)
Goal of this master thesis is to introduce and bring up basics and principles of NetCOPE framework in many details using "first approach" method for exploration of its internal structures - mainly focusing on application core using VHDL for focus itself. Furthermore, this knowledge is used for design and implementation of filtration system for network traffic with more details within phase of design in VHDL language.
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