National Repository of Grey Literature 2 records found  Search took 0.00 seconds. 
Acceleration of NAT and Packet Filter in FPGA for 10G Networks
Orsák, Michal ; Kořenek, Jan (referee) ; Viktorin, Jan (advisor)
This thesis deals with the design of a universal hardware acceleration unit for packet filtering in FPGA for 10G networks. Maximum count of rules is greatly increased by the use of external QDR-II memory. Parameters of accelerator are suitable for NAT, packet filtering and lawful interceptions. The platform uses variable number of processing units. One of them controls accelerator by USB port. The rest is used for network processing.
Acceleration of NAT and Packet Filter in FPGA for 10G Networks
Orsák, Michal ; Kořenek, Jan (referee) ; Viktorin, Jan (advisor)
This thesis deals with the design of a universal hardware acceleration unit for packet filtering in FPGA for 10G networks. Maximum count of rules is greatly increased by the use of external QDR-II memory. Parameters of accelerator are suitable for NAT, packet filtering and lawful interceptions. The platform uses variable number of processing units. One of them controls accelerator by USB port. The rest is used for network processing.

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