National Repository of Grey Literature 1 records found  Search took 0.01 seconds. 
Implementation of tunable digital filter into FPGA
Štěpán, Matěj ; Pristach, Marián (referee) ; Dvořák, Vojtěch (advisor)
Proposed bachelor thesis is focused on the design of an IIR filter. This work presents common structures of IIR filters including cascaded SOS structure. The outcome of this work is a summary of theory, assessment of the transfer function coefficients generated by the Filter Designer tool for a tunable IIR filter implemented on an FPGA and finally an implementation of a filter described in VDHL.

See also: similar author names
1 Štěpán, M.
11 Štěpán, Marek
3 Štěpán, Martin
2 Štěpán, Michael
2 Štěpán, Michal
7 Štěpán, Miroslav
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