National Repository of Grey Literature 60 records found  beginprevious51 - 60  jump to record: Search took 0.01 seconds. 
Magnetic field Supported Discharge Based Plasma Sources
Havlíček, Josef ; Kudrna, Pavel (advisor) ; Tichý, Milan (referee)
Main aim of this work was measurement of a floating potential fluctuations in the cylindrical magnetron in classical configuration in neon. Two Langmuir probes were used for measurement of wave vector. The following values were measured: pressure p in range 1-7 Pa, magnetic induction B in range 10-40 mT, discharge current I in range 5-100 mA, discharge voltage U and floating potential Uf. Fluctuations were described by dependencies of power spectral density on frequency S(f) and by histograms S(k,f), where k is wave vector. Several discharge modes were observed in the magnetron. These are characterized by different values of discharge voltage, electric field in positive column, magnitude of the floating potential etc. The discharge conditions, where peaks were observed in spectra, were determined. Only one peak with frequency in range 4-16 kHz was mostly observed. Most of these peaks had zero wave vector in histogram S(k,f), i.e. the floating potential synchronously oscillated in the whole discharge area. For some discharge conditions histograms with non-zero wave vector for noise background were observed.
Extension for Xilinx System Generator - logarithmic arithmetic blockset
Líčko, Miroslav ; Métais, B. ; Tichý, Milan ; Matoušek, Rudolf
The paper introduces support of floating point(FP) data format for the Xilinx System Generator (XSG) using logarithmic arithmetic. This type of arithmetic seems to be one of the promising ways to solve FP sort of DSP problems in practice. Our 32-bit high-speed logarithmic arithmetic (HSLA) keeps the accuracy according to IEEE 754 and speed up some kinds of FP algorithms. Promising is 19-bit equivalent utilised int this paper. It offers reasonable precision for the practical use and has min.HW requirements.
Prototyping of DSP algorithms on FPGA
Líčko, Miroslav ; Tichý, Milan ; Heřmánek, Antonín ; Matoušek, Rudolf ; Pohl, Zdeněk
Poster describes an algorithm development process for FPGA. The process is shown on the example of an implementation of the QR RLS algorithm.

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