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Implementation of Digital Circuit for High-Speed Network Communication in FPGA
 Kondys, Daniel ; Cíbik, Peter (oponent) ; Smékal, David (vedoucí práce)
Network cards with a hardware acceleration feature are a popular solution for meeting the ever-increasing demands for throughput in high-speed networks. Utilizing the FPGA chips as the hardware acceleration elements, this thesis presents a generic and highly modular digital circuit for FPGA that manages data transfers in form of Ethernet frames at rates reaching up to 400 Gbps. High-end FPGAs often contain hard IP blocks that simplify communication over the Ethernet protocol. The target FPGAs Intel Stratix 10 and Intel Agilex contain the E- and F-tile hard IP blocks for Ethernet, respectively. Before explaining the architecture of the designed digital circuit, it focuses on the theoretical background describing the basic functions of the Ethernet protocol, the given Intel FPGAs and the provided Ethernet hard IP blocks. After explaining its design and implementation, the thesis describes the steps taken during verification and hardware tests executed on platforms with the given FPGAs. The results of these tests indicated a successful implementation, as the data rate of 400 Gbps was reached. This digital circuit aims to be a part of the FPGA design for the XpressSX AGI-FH400G network card (among others) created by companies CESNET z.s.p.o and REFLEX CES.
Úplný záznam
Implementation of Digital Circuit for High-Speed Network Communication in FPGA
 Kondys, Daniel ; Cíbik, Peter (oponent) ; Smékal, David (vedoucí práce)
Network cards with a hardware acceleration feature are a popular solution for meeting the ever-increasing demands for throughput in high-speed networks. Utilizing the FPGA chips as the hardware acceleration elements, this thesis presents a generic and highly modular digital circuit for FPGA that manages data transfers in form of Ethernet frames at rates reaching up to 400 Gbps. High-end FPGAs often contain hard IP blocks that simplify communication over the Ethernet protocol. The target FPGAs Intel Stratix 10 and Intel Agilex contain the E- and F-tile hard IP blocks for Ethernet, respectively. Before explaining the architecture of the designed digital circuit, it focuses on the theoretical background describing the basic functions of the Ethernet protocol, the given Intel FPGAs and the provided Ethernet hard IP blocks. After explaining its design and implementation, the thesis describes the steps taken during verification and hardware tests executed on platforms with the given FPGAs. The results of these tests indicated a successful implementation, as the data rate of 400 Gbps was reached. This digital circuit aims to be a part of the FPGA design for the XpressSX AGI-FH400G network card (among others) created by companies CESNET z.s.p.o and REFLEX CES.
Úplný záznam

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