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Design of Superscalar RISC-V Processor
Salvet, Dominik ; Šimek, Václav (oponent) ; Jaroš, Jiří (vedoucí práce)
This thesis deals with designing and implementing a superscalar RISC-V processor microarchitecture focused on environments with constrained resources. For that, the microarchitecture exposes a dual-issue seven-stage pipeline with in-order instruction execution. It is described in SystemVerilog and can be easily simulated on a computer. Using prepared tools, the created processor model runs RISC-V assembly programs compiled by GCC. Based on conducted testing without special compiler assistance, the processor executes 0.88 instructions per cycle on average, providing 22.6 % higher performance than its scalar counterpart. Considering that the microarchitecture also avoids unnecessary specialization, it provides a good base that can be further extended and optimized based on the profiling of expected programs, leading to optimal performance and use of resources.

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