|
|
Nová metoda emulace obvodu zachovávající strukturu a časování obvodu
Kafka, Leoš
This paper presents an emulation technique that allows to preserve structure and optionally timing of an emulated circuit according to a target technology. The technique is compatible with fault injection techniques based on circuit instrumentation or partial runtime reconfiguration, and it allows to emulate timing parameters of the circuit through an introduction of a virtual time. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments.
|
|
| |
|
| |
|
|
Design Retiming na HDL úrovni
Kafka, Leoš ; Matoušek, Rudolf
This paper deals with an improvement of design timing characteristics by modification at the high abstraction level of the system description. Some synthesis tools such as Synplify Pro provide timing optimizations, called pipelining and retiming. These techniques help the designer unify delay slacks at different inputs, which results in higher system clock frequencies of the produced circuit.
|
|
|
Injektor poruch pro TSC obvody založený na FPGA
Kafka, Leoš
Newer FPGA devices are more susceptible to faults, especially transient faults. Some kind of concurrent error detection approach has to be used to avoid system failure due to these aults. To obtain the totally self checking property is the goal in most cases, but it's often impossible. It's useful to evaluate numbers of detectable and undetectable faults. An FPGA-based fault injector capable to get these values is presented in this paper. It's implemented in Atmel FPSLIC and uses dynamic reconfiguration.
|
guest ::
RSS feed.