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Packet generator on the FPGA platform
Bari, Lukáš ; Blažek, Petr (referee) ; Smékal, David (advisor)
The thesis deals with the theory and design of the network traffic generator on the FPGA platform. The VHDL programming language is used for the description. The work involves getting acquainted with the development processes and design tools needed to create the overall project. It also includes familiarity with the necessary FPGA, NetCOPE and COMBO cards. Based on this information, was designed, tested and implemented packet generator project for the Combo-80G card. For implementation was used framework from NetCOPE.
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Design and implementation of Twofish cipher on the FPGA network card
Cíbik, Peter ; Martinásek, Zdeněk (referee) ; Smékal, David (advisor)
This bachelor thesis deals with implementation of block cipher Twofish on the FPGA platform in VHDL language. The teoretical introduction explains basics of cryptography and symetric ciphers block operation modes, FPGA platform and introduction to VHDL language. In the next part the Twofish cipher, its components and flow are being dis- cussed in depth. Subsequently describes design of Twofish cipher in VHDL language and induvidual steps in this process. The last part deals with own implementation on hardware card with FPGA chip and summarizes reached goals.
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Implementation of matrix decomposition and pseudoinversion on FPGA
Röszler, Pavel ; Rajmic, Pavel (referee) ; Smékal, David (advisor)
The purpose of this thesis is to implement algorithms of matrix eigendecomposition and pseudoinverse computation on a Field Programmable Gate Array (FPGA) platform. Firstly, there are described matrix decomposition methods that are broadly used in mentioned algorithms. Next section is focused on the basic theory and methods of computation eigenvalues and eigenvectors as well as matrix pseudoinverse. Several examples of implementation using Matlab are attached. The Vivado High-Level Synthesis tools and libraries were used for final implementation. After the brief introduction into the FPGA fundamentals the thesis continues with a description of implemented blocks. The results of each variant were compared in terms of timing and FPGA utilization. The selected block has been validated on the development board and its arithmetic precision was analyzed.
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Network traffic and cyber attacks generator on the FPGA platform
Heriban, Radoslav ; Smékal, David (referee) ; Lieskovan, Tomáš (advisor)
This thesis is focused on the most common and every day more popular threat of DoS attacks. All networks are vulnerable to this kind of attack, and with growing popularity and intensity it shouldn't be underestimated. The goal of this thesis was creating hardware accelerated generator of DoS traffic intented for testing our own networks and identifying the risks. FPGA technology is used for this task, since it has proven to be more effective way of prototyping hardware design then developing ASIC. The language used to describe desired design behavior is VHDL. Designed ICMP and UDP flood attacks are simulated in Xilinx ISE development environment. Description of problems faced before any result was reached is also included for future researchers interested in similar projects.
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Web application for testing web server vulnerabilities
Šnajdr, Václav ; Burda, Karel (referee) ; Smékal, David (advisor)
The Master’s Thesis deals with the design and implementation of a web application for testing the security of SSL/TLS protocols on a remote server. The web application is developed in the Nette framework. The theoretical part describes SSL/TLS protocols, vulnerabilities, recommendations and technologies used in the practical part. The practical part is devoted to the creation of a web application with the process of using automatic scripts to test and display the results on the website with a rating of A+~to~C. The web application also displays a list of detected vulnerabilities and their recommendations.
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Network traffic analysis on FPGA network card
Crháková, Marie ; Lieskovan, Tomáš (referee) ; Smékal, David (advisor)
Bachelor thesis contains description of ISO/OSI and TCP/IP, then is focused on packet headers of the protocols IP, TCP and UDP. After that is analysed the FPGA from the company Xilinx with network interface card from Netcope Technologies and their functions defined by Firmware Developer´s Manual. Finally the studied informations was used for create the program for counting packets, that was simulated and synthesized for field programmable gate array through Vivado.
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Postquantum cryptography on FPGA
Kek, Sanjin ; Gerlich, Tomáš (referee) ; Smékal, David (advisor)
Subject of this bachelor thesis is postquantum cryptography on FPGA. Focus of theoretical part is to acquaint the reader with FPGA technology, basic principles of VHDL language, current situation in the field of postquantum cryptography and postquantum digital signing scheme CRYSTALS-Dilithium. Increased attention is paid to this scheme. Algorithms needed for function of the scheme, such as SHAKE, NTT and smaller operations used for public key compression, are described. Practical part contains hardware implementation of expandable output function SHAKE and smaller operations, such as Decompose, UseHint, Power2Round and others.
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Implementation of Digital Circuit for High-Speed Network Communication in FPGA
Kondys, Daniel ; Cíbik, Peter (referee) ; Smékal, David (advisor)
Vysokorychlostní síťové karty často obsahují prvky pro hardwarovou akceleraci, která jim umožní efektivně zpracovávat data i při velmi vysokých rychlostech. Tato práce se zabývá tvorbou digitálního obvodu pro FPGA, který bude přenášet Ethernetové rámce rychlostí až 400 Gb/s. K tomu využívá bloky duševního vlastnictví pro Ethernet, které jsou součástí moderních FPGA čipů od firmy Intel. Jedná se o FPGA Stratix 10, které obsahuje bloky duševního vlastnictví typu E-tile, a Agilex, které obsahuje bloky duševního vlastnictví typu F-tile. Před vlastním návrhem se práce zabývá teoretickým rozborem standardu Ethernet a činnostmi jednotlivých podvrstev, popisuje vybrané FPGA čipy a zabývá se i NDK platformou, do níž bude vytvořený obvod zapojen. Praktická část spočívá v konfiguraci daných duševních bloků pro Ethernet a jejich integrací do vytvářeného obvodu. Nakonec jsou popsány metody pro ověření funkčnosti vytvořeného obvodu. Ty zahrnují verifikaci a testy na platformách s danými FPGA čipy. Výsledky ukazují, že vytvořený obvod je funkční a dosahuje rychlosti i 400 Gb/s. Jeho využití spočívá zejména v poskytnutí komunikace přes Ethernet pro digitální obvod, který bude dodáván jako součást firmwaru pro síťovou kartu XpressSX AGI-FH400G vyvinutou sdružením CESNET z.s.p.o a společností REFLEX CES.
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Traffic detection and analysis using SSL/TLS
Hutar, Jan ; Dvořák, Jan (referee) ; Smékal, David (advisor)
This diploma thesis deals with a detection and analysis of secure connections of electro- nic communication through SSL/TLS protocols. The thesis begins with introduction to SSL/TLS protocols. Thereafter, an analysis of messages used to establish secure con- nections using STARTTLS and postal protocols SMTP, POP3, and IMAP was made. Metadata detection and extraction of secured simplex and duplex connections take place using deep packet inspection tools. The tool of choice is the nDPI library from the Ntop project. The library was extended to detect the connections and extract the metadata based on studies and analysis of transmitted messages. Finally, testing is performed on a training data set and a basic analysis of acquired metadata is made.
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P4 cryptographic primitive support
Cíbik, Peter ; Malina, Lukáš (referee) ; Smékal, David (advisor)
This diploma thesis deals with the problem of high-speed communication security which leads to the usage of hardware accelerators, in this case high-speed FPGA NICs. Work with simplification of development of FPGA hardware accelerator applications using the P4 to VHDL compiler. Describes extension of compiler of cryptographic external objects support. Teoretical introduction of the thesis explains basics of P4 language and used technologies. Describes mapping of external objects to P4 pipeline and therefore to FPGA chip. Subsequently deals with cryptographic external object, compatible wrapper implementation and verification of design. Last part describes implementation and compiler extension, cryptographic external object support and summarizes reached goals.
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