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Implementation of Fast Fourier Transformation on Transport Triggered Architecture
 Žádník, Jakub ; Slovák, Jiří (oponent) ; Maršálek, Roman (vedoucí práce)
The thesis proposes an energy-efficient processor architecture for computing a Fast Fourier Transform (FFT) using a Transport Triggered Architecture (TTA) template. The architecture was specifically tailored to a custom instruction schedule using several custom functional units (FUs). The instruction schedule for computing the algorithm was developed in a way that most of the computation is done in a loop containing only one instruction word. This word is stored into an instruction loop buffer which is more power-efficient than a regular memory storage. Thus a power consumption can be lowered. A timed model of the processor and the instruction schedule were developed, verified the approach and suggested further improvements. Python programs for generating referencing and an automatic verification of the timed models were developed to aid the design process.
Úplný záznam
Implementation of Fast Fourier Transformation on Transport Triggered Architecture
 Žádník, Jakub ; Slovák, Jiří (oponent) ; Maršálek, Roman (vedoucí práce)
The thesis proposes an energy-efficient processor architecture for computing a Fast Fourier Transform (FFT) using a Transport Triggered Architecture (TTA) template. The architecture was specifically tailored to a custom instruction schedule using several custom functional units (FUs). The instruction schedule for computing the algorithm was developed in a way that most of the computation is done in a loop containing only one instruction word. This word is stored into an instruction loop buffer which is more power-efficient than a regular memory storage. Thus a power consumption can be lowered. A timed model of the processor and the instruction schedule were developed, verified the approach and suggested further improvements. Python programs for generating referencing and an automatic verification of the timed models were developed to aid the design process.
Úplný záznam

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