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Serial communication peripheries development in FPGA
Štraus, Pavel ; Adamec, Filip (referee) ; Frýza, Tomáš (advisor)
This bachelor’s thesis is about two peripheries. First periphery creates from input parallel signals one output serial signal. This serial signal contains a start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count is set with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. Of course we have choice between even parity bit or odd parity bit. After parity bit there is one stop bit or there are two stop bits. Second periphery realizes I2C bus. This communication is between two devices. First device is called master and creates the communication with second device called slave. For communication there are two bidirectional lines. The first line is called SDA, which is a serial data line and second line is a serial clock line called SCL. Communication begins with a start condition. That means line SDA go from high to low while SCL is high and communication is terminate with a stop condition. That means line SDA go from low to high while SCL is high. The peripheries are programming in VHDL language and implemented in FPGA device. After successful simulation in free software ISE WebPACK the peripheries was realized in the development board V2MB1000 with device XC2V1000.
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Processor controlled backup power supply
Hořák, Jan ; Štraus, Pavel (referee) ; Kubíček, Michal (advisor)
This thesis describes the design of a processor controlled small battery backup power supply. The aim is to design a device which can recharge many kinds of mobile devices with a battery capacity up to 2Ah. The main control element is a microprocessor that records operating data of the power supply and stores in onto an SD card. Portability and durability were taken into account during the design. The result is completely designed and build a backup power supply, including program for its microcontroller.
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FPGA based sound card for PC
Štraus, Pavel ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.
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Processor controlled backup power supply
Hořák, Jan ; Štraus, Pavel (referee) ; Kubíček, Michal (advisor)
This thesis describes the design of a processor controlled small battery backup power supply. The aim is to design a device which can recharge many kinds of mobile devices with a battery capacity up to 2Ah. The main control element is a microprocessor that records operating data of the power supply and stores in onto an SD card. Portability and durability were taken into account during the design. The result is completely designed and build a backup power supply, including program for its microcontroller.
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Serial communication peripheries development in FPGA
Štraus, Pavel ; Adamec, Filip (referee) ; Frýza, Tomáš (advisor)
This bachelor’s thesis is about two peripheries. First periphery creates from input parallel signals one output serial signal. This serial signal contains a start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count is set with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. Of course we have choice between even parity bit or odd parity bit. After parity bit there is one stop bit or there are two stop bits. Second periphery realizes I2C bus. This communication is between two devices. First device is called master and creates the communication with second device called slave. For communication there are two bidirectional lines. The first line is called SDA, which is a serial data line and second line is a serial clock line called SCL. Communication begins with a start condition. That means line SDA go from high to low while SCL is high and communication is terminate with a stop condition. That means line SDA go from low to high while SCL is high. The peripheries are programming in VHDL language and implemented in FPGA device. After successful simulation in free software ISE WebPACK the peripheries was realized in the development board V2MB1000 with device XC2V1000.
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FPGA based sound card for PC
Štraus, Pavel ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
This project deals with implementation of a first order Sigma–Delta AD converter on the FPGA. This ADC is design for an audio signal processing. ADC is build up partially from digital blocks implemented in FPGA (programmed using VHDL) and from few analog components placed external to FPGA. Output from ADC is PCM signal. Data from ADC is created UDP datagram, which is sent to PC via network connection. Income data are received in created program, which save data to text file. This text file is processing in MATLAB.
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Implementation of the BEDAUX System in a chosen Firm
Martínek, David ; Dvořák, Jiří (advisor) ; Štraus, Pavel (referee)
The thesis is about implementation of Bedaux's system at company Laufen CZ, and its influence of company even from work productivity and cost viewpoints. In first part the Bedeux's system is teoretically described as base for practical part of the thesis. In practical part is described and later evaluated the process of implementation with the results even for workers and company. By using these results from practical part the recommendations are introduced to improve Bedeux's system in company. In final part the thesis is evaluated as complex.
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