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Network traffic processing at very high speed
Cabal, Jakub ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Different network devices require processing of the network traffic. To process the network traffic, it is necessary to parse headers of particular protocols packed in incoming ethernet frames. The processed headers can be repackaged to ethernet frames and sent back to the network. The goal of this thesis is to design and implement a circuit for analysis and parsing of ethernet frames, together with circuit for deparsing ethernet frames. The circuits are designed for throughputs of up to 400 Gb/s. The circuits are implemented for the FPGA technology.
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Hardware Acceleration of Extraction and Merging of Items from Packet Headers
Brázda, Mikuláš ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
Almost every device on the network needs to extract some fields from the packet headers for its operation, perform operations on them, and forward the reassembled packet. This processing must be implemented at a speed corresponding to the line speed. On high-speed networks, specialized circuits are used to meet this requirement. As the demands on network flexibility increase, so do the demands on the flexibility of these circuits. However, making changes to the hardware description languages is complex and time consuming. This work therefore deals with the implementation of circuits for extraction and subsequent merging of packet header items using high-level synthesis.
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Hardware Acceleration of Extraction and Merging of Items from Packet Headers
Brázda, Mikuláš ; Kekely, Lukáš (referee) ; Martínek, Tomáš (advisor)
Almost every device on the network needs to extract some fields from the packet headers for its operation, perform operations on them, and forward the reassembled packet. This processing must be implemented at a speed corresponding to the line speed. On high-speed networks, specialized circuits are used to meet this requirement. As the demands on network flexibility increase, so do the demands on the flexibility of these circuits. However, making changes to the hardware description languages is complex and time consuming. This work therefore deals with the implementation of circuits for extraction and subsequent merging of packet header items using high-level synthesis.
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Network traffic processing at very high speed
Cabal, Jakub ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Different network devices require processing of the network traffic. To process the network traffic, it is necessary to parse headers of particular protocols packed in incoming ethernet frames. The processed headers can be repackaged to ethernet frames and sent back to the network. The goal of this thesis is to design and implement a circuit for analysis and parsing of ethernet frames, together with circuit for deparsing ethernet frames. The circuits are designed for throughputs of up to 400 Gb/s. The circuits are implemented for the FPGA technology.
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