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Optimalization of CMOS Chip Interconnection Process for Higher Current Load
Novotný, Marek ; Mach,, Pavel (referee) ; Hulenyi,, Ladislav (referee) ; Szendiuch, Ivan (advisor)
This work deals with silicon chip interconnection with a view to high current up to 10A. A wire bonding method is used for interconnection. The first part of investigation is focused on the modeling and simulation by the help of program ANSYS. Thermo mechanical stressing and current density is important parts of this research. Stress and current density distribution are results of the first part. The experimental part describes transition resistance, electro migration and thermal process in the connection of wire and chip pad. A controlled current source (0 – 10A) is used for measurement. The current source makes it possible to 4-point method measurement with sampling rate 1,5MHz.
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Problems of measurement and evaluation of transient resistance in electrical engineering
Štěpanovský, Libor ; Cipín, Radoslav (referee) ; Veselka, František (advisor)
The aim of the Bachelor Thesis is to introduce the revisions to electrical wirings and equipment, to get familiarized with the problems of transient resistance and with measurement of transient resistance in electrical engineering. The first part of the Thesis describes various types of revisions, the procedure to carry out revisions and the methodology that must be followed during the revision. The second part is dedicated to transient resistance. It mentions factors which influence the magnitude of transient resistance, methods used to determine the magnitude of transient resistance and a practical demonstration of a transient resistance measurement.
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Problems of measurement and evaluation of transient resistance in electrical engineering
Štěpanovský, Libor ; Cipín, Radoslav (referee) ; Veselka, František (advisor)
The aim of the Bachelor Thesis is to introduce the revisions to electrical wirings and equipment, to get familiarized with the problems of transient resistance and with measurement of transient resistance in electrical engineering. The first part of the Thesis describes various types of revisions, the procedure to carry out revisions and the methodology that must be followed during the revision. The second part is dedicated to transient resistance. It mentions factors which influence the magnitude of transient resistance, methods used to determine the magnitude of transient resistance and a practical demonstration of a transient resistance measurement.
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Optimalization of CMOS Chip Interconnection Process for Higher Current Load
Novotný, Marek ; Mach,, Pavel (referee) ; Hulenyi,, Ladislav (referee) ; Szendiuch, Ivan (advisor)
This work deals with silicon chip interconnection with a view to high current up to 10A. A wire bonding method is used for interconnection. The first part of investigation is focused on the modeling and simulation by the help of program ANSYS. Thermo mechanical stressing and current density is important parts of this research. Stress and current density distribution are results of the first part. The experimental part describes transition resistance, electro migration and thermal process in the connection of wire and chip pad. A controlled current source (0 – 10A) is used for measurement. The current source makes it possible to 4-point method measurement with sampling rate 1,5MHz.
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