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A Generator of Arithmetic Circuits
Klhůfek, Jan ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor)
The aim of this bachelor thesis is to present the design and implementation of an arithmetic circuit generator. The generator focuses on generating various output representations of arithmetic circuits in flattened and hierarchical forms using the Python programming language. The work first deals with the specification of HW structures of individual arithmetic circuits and the corresponding ways of describing these structures into various representations. Followed by an introduction to the concept and details of the implementation of a tool called ArithsGen, which is able to generate arithmetic circuits and export them to various output representations. The output representations are then used for fast and simple simulation of the designed circuits (C), to describe the hardware structures and perform logic synthesis (Verilog), to formal verify the designs (BLIF) or to globally optimize the circuits using the evolutionary strategy (CGP). Finally, the generated representations were individually tested and compared with each other using the results obtained from logic synthesis.
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Arithmetic Circuit Generator
Bolješik, Michal ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
The goal of this thesis is to design and implement a tool that would be able to generate a description of various types of arithmetic circuits, such as adders and multipliers, that are involved in more complex systems (filters, transformations, etc.). The first part of the thesis deals with analysis of different types of adders and multipliers on either theoretical or practical level. In the second part there is a description of the design and implementation of the tool created in Python language. On base of parameters, the tool is able to generate hierarchical or flattened description of various circuits in formats aimed for visualization, simulation and validation. In the end, the tool is used to compare different designs of adders and multipliers.
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A Generator of Arithmetic Circuits
Klhůfek, Jan ; Vašíček, Zdeněk (referee) ; Mrázek, Vojtěch (advisor)
The aim of this bachelor thesis is to present the design and implementation of an arithmetic circuit generator. The generator focuses on generating various output representations of arithmetic circuits in flattened and hierarchical forms using the Python programming language. The work first deals with the specification of HW structures of individual arithmetic circuits and the corresponding ways of describing these structures into various representations. Followed by an introduction to the concept and details of the implementation of a tool called ArithsGen, which is able to generate arithmetic circuits and export them to various output representations. The output representations are then used for fast and simple simulation of the designed circuits (C), to describe the hardware structures and perform logic synthesis (Verilog), to formal verify the designs (BLIF) or to globally optimize the circuits using the evolutionary strategy (CGP). Finally, the generated representations were individually tested and compared with each other using the results obtained from logic synthesis.
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Arithmetic Circuit Generator
Bolješik, Michal ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
The goal of this thesis is to design and implement a tool that would be able to generate a description of various types of arithmetic circuits, such as adders and multipliers, that are involved in more complex systems (filters, transformations, etc.). The first part of the thesis deals with analysis of different types of adders and multipliers on either theoretical or practical level. In the second part there is a description of the design and implementation of the tool created in Python language. On base of parameters, the tool is able to generate hierarchical or flattened description of various circuits in formats aimed for visualization, simulation and validation. In the end, the tool is used to compare different designs of adders and multipliers.
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