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UVM Verification of DMA Medusa System
 Petruška, Zdenko ; Martínek, Tomáš (referee) ; Kekely, Lukáš (advisor)
This thesis describes design and implementation of verification environment for system DMA Medusa. DMA Medusa is hardware system used for high speed transmissions between network card and RAM. Verification environment is developed in SystemVerilog using UVM. Environment is designed with intention to find functional bugs using top level random stimulus. Testbench requirements have been defined prior to its implementation. Requirements are based on system specification and previous version of testbench. Previous version has been based on different methodology. New testbench implements the functionality of previous one. In addition, some functionality has been exteded. Implemented testbench extends previous memory model by serving memory requests in random order. It also implements functional coverage focused on communication with memory and network card. Goal of functional coverage is to monitor quality of generated stimulus.
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