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National Repository of Grey Literature 1 records found  Search took 0.00 seconds. 
Large area delayering
 Mezera, Petr ; Adámek, Martin (referee) ; Búran, Martin (advisor)
This work deals with the design of a model workflow for the planar delayering of large areas. The work describes the general design of integrated circuits, as well as the most basic possibilities of their packaging. Then, an overview of the methods used for delayering semiconductor chips, their advantages, principles or limitations was made. Current trends in semiconductor chip delamination are presented. The FIB and BIB methods are then discussed in detail. Furthermore, model workflows for planar layer delayering have been proposed. The methods were applied to prepared samples and the results were discussed, compared and measures for possible improvement were recommended.
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