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FPGA core for data displaying on computer monitor using VGA port
Pišl, Adam ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
The aim of this project is to perform the study of a driver for controlling computer monitor using VGA port. The driver is based on FPGA which is used to generate VGA signals. The main purpose of the project is to design a hardware core for gate array which can be used as part of some complex FPGA design to provide a comfortable user interface. The project describes the main part of the VGA driver – module for generating control signals and module for displaying text information that is sent from a PC via serial port interface.
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On-board computer for older car
Knápek, Mojmír ; Kubíček, Michal (referee) ; Pospíšil, Martin (advisor)
A thesis is about designing a device, which can add to older car some functions, which are now common like central locking, car-alarm, immobiliser and automatic turning lights on. There will be also solved sensors of input signals, their connecting to the microcontroller and ways to show outputs. In the end of thesis will be designed schematic and board.
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Microprocessor system IP core generator
Kerber, Rostislav ; Tošovský, Petr (referee) ; Kubíček, Michal (advisor)
This master’s thesis deal’s with VHDL programming language, ISE Webpack design system and PicoBlaze microprocessor. The thesis describes essentials of VHDL programming language and its application. A simple introduction to ISE Webpack design environment is given. The thesis describes common peripherals and the PicoBlaze processor is described too, including its parameters and implementation aspects. Finally the thesis describes IP generator for generating complex FPGA design including Picoblaze processor.
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Wideband 6GHz RF Signal Generator
Mička, Josef ; Kubíček, Michal (referee) ; Urbanec, Tomáš (advisor)
The goal of this thesis is a design of a wideband high frequency generator with an adjustable output amplitude. The generator is based on a frequency synthesizer ADF4355. The power level of an output signal is adjustable by an attenuator HMC1119. The created generator is accesisible trough an user-friendly control panel or by SCPI commands. Frequency synthesis can run in an integer mode or a fractional mode. The output signal has a very low phase noise when it is running in the integer mode.
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Communication between FPGA and computer - USB high speed
Kollár, Tomáš ; Kubíček, Michal (referee) ; Kolouch, Jaromír (advisor)
This bachelors thesis is about a possible interconnection method of FPGA (Field-Programmable Gate Array) chips with the PC through the USB 2.0 bus. These programmable arrays are very important nowadays mainly because of their high speed and high flexibility. Such properties make possible to use FPGAs in applications that require small data bandwidth and also which can utilize the whole bandwidth offered by the USB 2.0 bus. This thesis deals with possibility to use such transfer rate and its short description followed by the design of PCB layout. As the communication between the FPGA and the PC is made possible with the help of a microcontroller capable of handling such requests, I decided to include a short description of its functionality and working principle description in the thesis. The last part describes the communication through the GPIF interface for high-speed transfers.
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Program update of Zynq-based devices
Michálek, Branislav ; Buchta, Petr (referee) ; Kubíček, Michal (advisor)
Among many which are placed on modern embedded systems is also the need of storing multiple system boot image versions and the ability to select from them upon boot time, depending on a function which they provide. This thesis describes the development of a system update application for Xilinx Zynq-7000 devices. The application includes a simple embedded HTTP server for a remote file transfer. A client is allowed to upload the boot image file with the system update from either command line application or using the web page developed for this purpose.
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