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Verification of Function Blocks for FPGA
Kříž, Daniel ; Smékal, David (referee) ; Jedlička, Petr (advisor)
This master thesis is devoted to the issue of verification of function blocks for FPGA. The teoritical part of thesis describes the concept of verification, verification methodologies that provide the necessary tools for testing the design, and finally discusses the issue of Ethernet and its differences from the low-latency variant. The aim of the practical part of the master thesis is based on the acquired theoretical knowledge and selected verification methodology to build a verification environment, perform a thorough verification of the low-latency physical layer of Ethernet and finally measure the latency and throughput of this circuit.
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Cryptography on constrained devices
Šťovíček, Petr ; Jedlička, Petr (referee) ; Dzurenda, Petr (advisor)
The bachelor thesis analyzes the possibilities of applying cryptographic primitives and protocols to various computationally and memory constrained devices. It then implements a secure data collection system from sensors. In its theoretical part, the work examines individual cryptographic algorithms, the RIOT operating system and available methods of wireless data transmission. It then presents the results of performance tests of various cryptographic operations. On this basis, it designs and implements a system that ensures the confidentiality, authenticity and integrity of transmitted data.
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Noise meter and sound detector
Jedlička, Petr ; Novák, Marek (referee) ; Povalač, Aleš (advisor)
This work deals with design and construction of a noise meter, which measures sound pressure level. The device can be set either for weighting filter A or for weighting filter C considering the characteristics of human hearing, the device also allows two modes, fast and slow, depending on the rate of changes of sound pressure level. It tis possible to send measured data to a PC through a measuring application. The noise meter can be powered either by three AA batteries or by a PC through USB interface. The noise meter can be controlled by voice commands.
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Design of a modular miniaturized apparatus for ion trapping
Jedlička, Petr ; Pham, Minh Tuan ; Grim, Jakub ; Čížek, Martin ; Čepil, Adam ; Slodička, L. ; Číp, Ondřej
We are developing a new experimental apparatus for laser cooling of trapped ions, focusing on high electric field homogeneity, modularity and small size. The apparatus allows measurements with Coulomb crystals and easy modification for different experiments. The high homogeneity trap is created by electrospinning, while the modularity allows for the exchange of key parts. By miniaturizing the dimensions, we achieve a larger numerical aperture of the lens and a reduction in the size of the magnetic shielding. This portable apparatus offers new possibilities for ion studies and is promising for applications in satellite systems and reconnaissance satellites.
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Communication in a hardware accelerated circuit
Rosa, Michal ; Jedlička, Petr (referee) ; Smékal, David (advisor)
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks. Although one-time programmable (OTP) FPGAs are available, the dominant types are SRAM based which can be reprogrammed as the design evolves.
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Communication in a hardware accelerated circuit
Rosa, Michal ; Jedlička, Petr (referee) ; Smékal, David (advisor)
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. FPGAs can be reprogrammed to desired application or functionality requirements after manufacturing. This feature distinguishes FPGAs from Application Specific Integrated Circuits (ASICs), which are custom manufactured for specific design tasks. Although one-time programmable (OTP) FPGAs are available, the dominant types are SRAM based which can be reprogrammed as the design evolves.
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Random number generation on FPGA platform
Písek, Miroslav ; Jedlička, Petr (referee) ; Dobiáš, Patrik (advisor)
The bachelor's thesis deals with the implementation of a hardware random number generator on FPGA platform. It tries to explain the basic architecture and possible FPGA configuration. In the theoretical part, the principles of random number generators are further described and then the statistical tests through which we evaluate these generators. In the following section, the existing generators designed for FPGA platforms are summarized and analyzed. A closer measurement of freely available TRNG is also underway. In the final part, there is a description of the implementation of the own random number generator. Randomness verification takes place through the NIST statistical test suite.
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Smart VoIP doorbell
Čecháček, Šimon ; Jedlička, Petr (referee) ; Caha, Tomáš (advisor)
This bachelor thesis focuses on the extension of an existing VoIP communicator on a single board computer Raspberry Pi, which uses the SIP protocol. The thesis introduces, among other things, an extension for one-way video transmission and conditional relay switching. The resulting communicator is able to make a call with two-way communication, execute a defined code using DTMF codes after authorization of the called user and switch a relay. The entire device is housed in a box printed on a 3D printer. The IT security of the proposed solution has been analyzed and the code and 3D model of the chassis are available on GitHub.
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