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Postquantum cryptography on FPGA
Győri, Adam ; Jedlička, Petr (referee) ; Smékal, David (advisor)
This work describes the post-quantum algorithm FrodoKEM, its hardware implementation in VHDL and software simulation of implementation, subsequent implementation of the implementation on the FPGA process system. The work describes the issue of postquantum cryptography and VHDL programming language used to describe the functionality of hardware. Furthermore, the work deals with the functional implementation and simulation of all parts of the algorithm. Specifically, these are parts, key generation, encapsulation, and decapsulation. Algorithm implementation and simulations were performed in the Vivado software simulation environment, created by Xilinx. Subsequently, the synthesis and implementation was performed and the Intellectual property block was designed, the key part of which covered the functionality of the NEXYS A7 FPGA board was not available. The last part of the work deals with the workflow algorithm for implementation on FPGA board NEXYS A7.
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Software GNSS receiver
Jedlička, Petr ; Bobula, Marek (referee) ; Záplata, Filip (advisor)
The thesis deals with the analysis and the reception of the freely available signals of the navigation satellites in the L1 and E1 bands of the GPS and Galileo systems. The described signal reception sections include the process of the acquisition, the carrier frequency and phase synchronization and tracking, the spreading code phase tracking, the signal demodulation and the channel decoding. The simulation of the entire receiver is performed in MATLAB. The deeply analyzed signal reception component is the one responsible for the carrier phase and frequency synchronization and tracking. In that case, more methods and their comparison are usually listed. The signal reception component, which is responsible for the carrier phase and frequency tracking and the spreading code phase tracking, is also implemented in FPGA.
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Web application demonstrating lattice-based cryptography
Sečkár, Martin ; Jedlička, Petr (referee) ; Ricci, Sara (advisor)
Zámer tejto práce je vyvinúť a implementovať webovú aplikáciu demonštrujúcu kryptografiu založenú na mriežkach. Aplikácia bola vyvinutá použitím programovacieho jazyku Python a kontajnerizačnej platformy Docker. Špecifickejšie, implementované moduly používajú knižnicu Bokeh a vlastnú JavaScript funkcionalitu, ktorá rozširuje danú knižnicu Bokeh. Tieto moduly sú poskytované serverom Flask, kde taktiež prebiehajú všetky výpočty pomocou knižnice numPy. Aplikácia obsahuje tri moduly popisujúce problém najbližšieho vektora, problém učenia s chybami a Boyenov kryptografický protokol založený na predchádzajúcom probléme. Užívatelia majú možnosť vizualizovať dvojdimenzionálne mriežky a prevádzať vybrané výpočty. Zdrojový kód je jednoducho rozšíriteľný a môže slúžiť ako náučná platforma. Práca taktiež obsahuje inštalačný a používateľský manuál.
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RF analog fiber optic link
Kelbler, Petr ; Jedlička, Petr (referee) ; Drexler, Petr (advisor)
This thesis analyzes the problem of design analog fiber optic link for transmission high frequency signals. Analog fiber optic link will be used in system for detection and localization a partial discharge activity MOSAD-PD-UHF, where will replace existing solution with coaxial cables, which is not appropriate for highly noise environment. MOSAD-PD-UHF system is developed in department of theoretical and experimental electrical engineering. At the first, MOSAD-PD-UHF system and individual parts of optical chain are theoretical described. In following part are compared a few commercially available analog fiber optic link and design of chosen transmit and receive module are described. . The thesis final part deals with construction of optical link and measured parameters are discussed.
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Cryptographic algorithms on FPGA
Broda, Jan ; Jedlička, Petr (referee) ; Hajný, Jan (advisor)
The master thesis is focused on developing a demonstrator which is able to transmit data not only between operating system and network FPGA card with a UltraScale+ chip but also between two network FPGA cards. The theoretical part of the master thesis describes FPGA, developing on FPGA, programming languges that are used and develoment enviroment Vivado Design Suite. The demonstrator consists of two applications developed in C language which are used for communication between operating system and the network FPGA card and two components developed in VHDL langague which are used for communication throught a network module on the network FPGA card. The demonstrator allows inserting cryptographic algorithm which would work with transmitted data. For developing on the network FPGA card was used a Network Development Kit provided by a Liberouter team from CESNET association.
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Cryptographic Escape Room Game
Nosek, Ondřej ; Jedlička, Petr (referee) ; Ricci, Sara (advisor)
Tato bakalářská práce se zabývá implementací únikové hry ve formě webové aplikace. Tématem jednotlivých místností je kryptografie v mnoha podobách. Konkrétně se uživatel aplikace zabývá modulární aritmetikou, systémem pro šifrování dat včetně jeho menších částí, jako je u Advanced Encryption Standard, nebo také základy síťové bezpečnosti. Hlavními cíli bakalářské práce je seznámení se s tématem únikových her, webových aplikací a realizace webové aplikace. Úniková hra obsahuje celkem čtyři pokoje. Práce popisuje volbu technologií, na kterých aplikace bude postavena, a postup implementace jednotlivých místností včetně možností řešení úkolů. V samotném závěru pak shrnuje dosažené výsledky a cíle.
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Autonegotiation implementation for 25 - 100 Gbps Ethernet interfaces
Válek, Vladislav ; Jedlička, Petr (referee) ; Tomašov, Adrián (advisor)
This bachelor's thesis addresses the design of the auto-negotiation component for network interface cards controlled by FPGAs. Auto-negotiation function allows to advertise the available communication parameters, like the link speed, the transmission pause ability or Forward Error Correction (FEC) ability, by either side of the common link and determine the common abilities, which will be used to establish a connection. In the beginning, the internal parts of Xilinx UltraScale+ FPGA family are introduced with greater emphasis on the description of GTY transceivers. In the next chapter are introduced the mechanisms of auto-negotiation function as described in clause 73 of the IEEE 802.3-2018 standard. The design here is created for Ethernet interfaces running at speed 25~Gbps and is written in VHDL language. The next chapter describes the necessary steps which are required for the implementation on the FPGAs, where high-speed transceivers are in use. Function of the created design was then checked within a simulation and the correspondent results are also provided in this thesis. In the end, the testing of the designed auto-negotiation component took place for which the network card with Vitex 7 UltraScale+ FPGA was used. The testing process includes the use of the Integrated Logic Analyzer (ILA) which was inserted into final design. The achieved results from testing of both, the auto-negotiation process and surrounding physical layer processes, are described here with proper commentary.
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Emergency responce planing in approved traning organization
Jedlička, Petr ; Švec, Michal (referee) ; Šplíchal, Miroslav (advisor)
This master‘s thesis is focused on the creation of the Emergency Response Plan (ERP) for an Approved Training Organisation (ATO). The first part of this thesis describes aviation organisations and other transport organisations that require Safety management system. The second part analyses requirements for documentation and regulations for applying Emergency Response Plan. In the third section there is an ERP general manual which helps ATO with the creation of the document. The last part contains the ERP created for a model ATO with the help of the general manual from the third chapter.
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Postquantum Cryptography on the FPGA Platform
Dobiáš, Patrik ; Jedlička, Petr (referee) ; Malina, Lukáš (advisor)
This master thesis deals with the hardware implementations of post-quantum cryptogra- phy schemes on FPGA platforms. After the initial comparison of the candidate schemes for NIST standardization and the analysis of the previous work focusing on these schemes, Crystals-KYBER scheme was chosen and implemented. All scheme algorithms have been implemented inside a single component, minimizing resource utilization. The results of this implementation were analyzed and compared with the existing implementations. At the end of this work, the implemented scheme was deployed on Virtext UltraScale+ and tested for the use during mutually authenticated key exchange (AKE).
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Controller of three-axis nano-metric manipulator
Pernica, Lukáš ; Jedlička, Petr (referee) ; Drexler, Petr (advisor)
This diploma thesis describes the piezoelectric phenomenon and its use for positioning with nanometric precision in laboratory use. In the thesis is description of direct and indirect piezoelectric phenomenon, various types of piezoelectric actuators and ways of their control with the aim of eliminating their hysteresis. The goal is to design a controller for piezo actuator built in the three-axis nanometric manipulator Thorlabs MAX341/M.
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