National Repository of Grey Literature 3 records found  Search took 0.04 seconds. 
Nová metoda emulace obvodu zachovávající strukturu a časování obvodu
Kafka, Leoš
This paper presents an emulation technique that allows to preserve structure and optionally timing of an emulated circuit according to a target technology. The technique is compatible with fault injection techniques based on circuit instrumentation or partial runtime reconfiguration, and it allows to emulate timing parameters of the circuit through an introduction of a virtual time. An area and timing overhead due to preserving the circuit structure and parameters of basic delay elements are evaluated by experiments.
Simulátor chyb založený na programovatelném logickém obvodu
Kafka, Leoš ; Novák, O.
This paper describes a simulator based an this technique and show that partial dynamic reconfiguration is an effective way of falut injection. Error-detection-code based CED circuits are used in experiments; the results of the experiments are reported.
Injektor poruch pro TSC obvody založený na FPGA
Kafka, Leoš
Newer FPGA devices are more susceptible to faults, especially transient faults. Some kind of concurrent error detection approach has to be used to avoid system failure due to these aults. To obtain the totally self checking property is the goal in most cases, but it's often impossible. It's useful to evaluate numbers of detectable and undetectable faults. An FPGA-based fault injector capable to get these values is presented in this paper. It's implemented in Atmel FPSLIC and uses dynamic reconfiguration.

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