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AUTOMATED TESTING OF 10GbE DEVICES
Avramović, Nikola ; Dvořák, Vojtěch (referee) ; Fujcik, Lukáš (advisor)
Tato práce se zabývá návrhem modelu pro funkční verifikaci a návrhem syntetizovatelného testru 10Gb Ethernet zařízení, které používají XGMII rozhraní. Pro popis modelu je použit programovací jazyk VHDL. Práce zahrnuje vytváření bus functional modelu a návrh testru, který se implementuje jako genericky self-test modul. Výsledný návrh umožňuje verifikaci a testování PHY a MAC vrstve. Pro implementaci testru byla použita vývojová deska DE5-Net osazena FPGA obvodem Stratix V GX od firmy Altera.
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Influence of the frame size on splitting ratio in the passive optical networks XG-PON
Kočí, Lukáš ; Horváth, Tomáš (referee) ; Münster, Petr (advisor)
The diploma thesis deals with the theoretical definition of passive optical networks, furthermore the description of methods of channel bundling in passive optical networks and the coexistence and migration between standards. The main essence of this work is the XG-PON (10-Gigabit-capable Passive Optical Network) standard. This standard is generally defined along with a description of the physical layer. The transport layer is detailed analysis. There is a description of conditions, under which the Optical Network Unit pass through, when is activated. Additionally, this diploma thesis focuses on the processes of connecting Optical Network Units to the Passive Optical Networks and the timing relationships between Optical Network Units and Optical Line Terminal. The simulations demonstrate that as the number of simultaneous connections to Optical Network Unit increase, longer wait time for each additional connection becomes. This also solves the collision conditions, that might arise in communication and the equalization delay. Finally, the diploma thesis deals with the influence of a refractive index on timing relationships.
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Multichannel HD-SDI digital video signal converter
Kučera, Stanislav ; Bobula, Marek (referee) ; Kubíček, Michal (advisor)
This master’s thesis deals with the design of six channel SD, HD and 3G HD-SDI digital video signal converter to 10-Gigabit Ethernet. In the introductory part, the conception of designed device is formulated. The theoretical background is provided in four chapters, where main standards and design rules related to digital electronics’ design are analyzed. The emphasis is placed on signal integrity at high-speed interconnects. There mostly practical examples, calculations and simulations are utilized. The design part contains thorough description of main subsystems’ design, implementation of FPGA, SDI input channels and 10-Gigabit Ethernet PHY. In the final part, the first tests and measurements of the build prototype are summarized. As an example, the comparison of signal integrity simulation to measurement is provided.
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ARM Cortex M4 Development board
Volek, Lukáš ; Macho, Tomáš (referee) ; Burian, František (advisor)
In this work I aimed at designing a universal system for testing either STM32F407/417 by STMicroelectronics and later various sensors and communication buses. The result then is a main board with many specific connectors for individual buses even with connectors making all I/O pins accessible at the same time. Thanks to advanced switching regulators the power supply is capable of accepting a wide range of sources like single Li-Ion cell, pair of alkaline cells, 12V Lead battery, common wall power adapters (both DC and AC up to 15 Vpp ), USB, laboratory power supplies with multiple outputs and finally POE (Power Over Ethernet). Supply voltages are supervised by voltage comparators with an optical signalisation. (It is possible to determine the sick branch without a measuring instrument and blowing components in the most cases.) Another important parameter was a robustness of the supply and communication lines. There is a number of TVSs, chokes, and big and low ESR capacitors A PC software is intended for a basic functionality demonstration only.
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An USB-Ethernet joystick convertor for mobile robot
Šutera, Libor ; Florián, Tomáš (referee) ; Burian, František (advisor)
This thesis describes the design of construction of the converter USB joystick on the Ethernet interface. In the first part are theoretically analyzed both protocols used for the converter. An analysis of current microprocessor trade and their possible using for application in this project. Next part including the specification of used microprocessor and all options of programming and debugging of the microprocessor. Another part deals with the detailed design of the hardware interface. The last part describes the software equipment of microprocessor and the final appreaciation of work.
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