National Repository of Grey Literature 2 records found  Search took 0.01 seconds. 
Laboratory kit for design work with Altera CPLD devices
Gajdošík, Petr ; obrany, Petr Bojda, Univerzita (referee) ; Kolouch, Jaromír (advisor)
In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The product is used for development and demonstration of applications in CPLD devices made by Altera company. The kit is designed for Altera programming cables and Presto (made by ASIX). Input signals are implemented by a set of switches and buttons on the board. Output states are displayed by LED diods, possibly connected to multiplex the display. The user can connect to external devices via external inputs. Thesis is also aimed at the design PCB of the laboratory kit, subsequent production, recovery and verification of compatibility ALTERA and PRESTO programmers. End of the thesis aims on working with the Quartus II design environment. In particular, it is a guide to working with templates and simulation of VHDL designs.
Laboratory kit for design work with Altera CPLD devices
Gajdošík, Petr ; obrany, Petr Bojda, Univerzita (referee) ; Kolouch, Jaromír (advisor)
In this thesis I aim at a design of the laboratory kit and study ways how to programme CPLD devices made by Altera company. The product is used for development and demonstration of applications in CPLD devices made by Altera company. The kit is designed for Altera programming cables and Presto (made by ASIX). Input signals are implemented by a set of switches and buttons on the board. Output states are displayed by LED diods, possibly connected to multiplex the display. The user can connect to external devices via external inputs. Thesis is also aimed at the design PCB of the laboratory kit, subsequent production, recovery and verification of compatibility ALTERA and PRESTO programmers. End of the thesis aims on working with the Quartus II design environment. In particular, it is a guide to working with templates and simulation of VHDL designs.

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