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Web Portal for VHDL Core Generator
 Poupě, Petr ; Kaštil, Jan (referee) ; Straka, Martin (advisor)
In this Bachelor thesis, activities which aim at developing web portal for an intuitive access to VHDL core generators are presented. The basic principles of methodology for generating VHDL descriptions of hardware checkers for communication protocols and RTL circuits are demonstrated together with their impact on the fault tolerant architectures. The main goal of this work is to develop user-friendly web environment which would facilitate the use of VHDL core generators. The specification and features of web portal are described together with implementation details and testing of final application. As the results of this thesis, the web portal based on PHP and MySQL database was created.
Detailed record
Web Portal for VHDL Core Generator
 Poupě, Petr ; Kaštil, Jan (referee) ; Straka, Martin (advisor)
In this Bachelor thesis, activities which aim at developing web portal for an intuitive access to VHDL core generators are presented. The basic principles of methodology for generating VHDL descriptions of hardware checkers for communication protocols and RTL circuits are demonstrated together with their impact on the fault tolerant architectures. The main goal of this work is to develop user-friendly web environment which would facilitate the use of VHDL core generators. The specification and features of web portal are described together with implementation details and testing of final application. As the results of this thesis, the web portal based on PHP and MySQL database was created.
Detailed record

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