National Repository of Grey Literature 3 records found  Search took 0.01 seconds. 
Playstation 1 Emulator with Higher Rendering Resolution
Stupka, Filip ; Šimek, Václav (referee) ; Jaroš, Jiří (advisor)
This thesis investigates the augmentation of visual fidelity in PlayStation 1 emulation by implementing advanced rendering techniques for higher resolution output. The study begins with a thorough analysis of the original hardware architecture, identifying components impacting graphical output. Focusing on developing a custom emulator, the research addresses challenges associated with upscaling graphics while maintaining compatibility with existing game software. The findings provide valuable insights for retro gaming enthusiasts and researchers, showcasing the successful implementation of a PlayStation 1 emulator with higher rendering resolution to preserve the legacy of classic games.
FPGA IP core for Sony IMX sensor interface
Musil, Milan ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
The diploma thesis deals with the implementation of the SLVS-EC interface into the FPGA. This interface is used in new SONY’s image sensors for high-speed data transmission. The introduction contains a description of the interface, its possible configurations and comparison with the sub LVDS interface used so far. This is followed by the selection of a suitable MPSoC with the Zynq Ultrascale+ architecture with focus to its hardware resources for receiving a high/speed signal. The main part of this thesis deals with the design of receiver for the SLVS-EC interface and decoding of the data. The raw image data is then stored in external RAM. At the end of this thesis is described the chosen methods of testing partial parts and overall design.
FPGA IP core for Sony IMX sensor interface
Musil, Milan ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
The diploma thesis deals with the implementation of the SLVS-EC interface into the FPGA. This interface is used in new SONY’s image sensors for high-speed data transmission. The introduction contains a description of the interface, its possible configurations and comparison with the sub LVDS interface used so far. This is followed by the selection of a suitable MPSoC with the Zynq Ultrascale+ architecture with focus to its hardware resources for receiving a high/speed signal. The main part of this thesis deals with the design of receiver for the SLVS-EC interface and decoding of the data. The raw image data is then stored in external RAM. At the end of this thesis is described the chosen methods of testing partial parts and overall design.

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