Original title: Stavový firewall v FPGA
Translated title: Stateful Firewall for FPGA
Authors: Žižka, Martin ; Kajan, Michal (referee) ; Puš, Viktor (advisor)
Document type: Master’s theses
Year: 2012
Language: cze
Publisher: Vysoké učení technické v Brně. Fakulta informačních technologií
Abstract: [cze] [eng]

Keywords: FPGA; NetCOPE; packet filtering; security; Stateful firewall; VHDL; bezpečnost; filtrování paketů; FPGA; NetCOPE; Stavový firewall; VHDL

Institution: Brno University of Technology (web)
Document availability information: Fulltext is available in the Brno University of Technology Digital Library.
Original record: http://hdl.handle.net/11012/53761

Permalink: http://www.nusl.cz/ntk/nusl-562450


The record appears in these collections:
Universities and colleges > Public universities > Brno University of Technology
Academic theses (ETDs) > Master’s theses
 Record created 2024-04-02, last modified 2024-04-03


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