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Implementation of a Boot Controller for Intel FPGAs
Hak, Tomáš ; Fukač, Tomáš (referee) ; Matoušek, Jiří (advisor)
This thesis touches the topic of using FPGA technology in the field of computer networks, specifically for hardware acceleration of network traffic processing on a network card developed by the CESNET association. FPGA technology is popular mainly due to the possibility to easily reconfigure the chip and fix any errors or update the firmware. The thesis first discusses the design and implementation of a new unit for Intel FPGA, which will be able to communicate with the external configuration flash memory of the chip featured on the card mentioned above. It then goes on to address the design and implementation of a software tool that will allow, via the newly implemented firmware unit, to load new configuration data into the flash memory and force reconfiguration of the FPGA chip using this newly loaded data. Towards the end of the thesis, the functionality of the newly implemented system is tested in practice.
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Packet Transmission at 100 Gb/s Ethernet
Hummel, Václav ; Dvořák, Milan (referee) ; Matoušek, Jiří (advisor)
The NetCOPE platform is used for rapid developement of hardware accelerated network applications on the family of COMBO cards. An essential part of this platform is output network module which helps designers to implement Data Link Layer of the OSI reference model, especially the MAC sublayer. This bachelor’s thesis focuses on design, implemen- tation and verification of such a module operating at speed 100 Gb/s. Furthemore, an appli- cation on the NetCOPE platform was created. It is designed for transmitting short samples of network traffic stored in QDR static memory. Transmission is controlled by precise ti- mestamps. The whole system was deployed on a COMBO card and verified by a network traffic analyzer.
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Application Specific Processor for Stateful Network Traffic Processing
Kučera, Jan ; Matoušek, Jiří (referee) ; Kekely, Lukáš (advisor)
This bachelor's thesis deals with the design and implementation of an application-specific processor for high-speed network traffic processing. The main goal is to provide complex system for hardware acceleration of various network security and monitoring applications. The application-specific processor (hardware part of the system) is implemented on an FPGA card and has been designed with respect to be used in 100 Gbps networks. The design is based on the unique combination of high-speed hardware processing and flexible software control using a new concept called Software Defined Monitoring (SDM). The performance and throughput of the proposed system has been verified and measured.
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Graphical User Interface for Packet Generator
Chromčák, Michal ; Kováčik, Michal (referee) ; Matoušek, Jiří (advisor)
According to increasing requirements on speed of different software and hardware components, there are solutions, which can, by principle, reach better parameters, then solutions commonly known. One of them is to use software with hardware acceleration on the field of generating synthetic network traffic. Exactly this way a packet generator was implemented, in current version without graphical user interface. But to let this system spread into the target group of users, there is need to implement also this interface. This bachelor's thesis describes proposal of graphical interface, its implementation in JavaFX programming language, testing on real users and tutorial demonstrating how to use this interface.
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Generator of IPv6 Tables
Lorenc, Marián ; Bartoš, Václav (referee) ; Matoušek, Jiří (advisor)
The increasing number of IPv6 prefixes in routing tables require creation of efficient lookup algorithms, which are adapted to the length of prefixes. To create and to test these algorithm,s it is necessary to have extensive tables, which currently do not exist. This thesis is about design and implementation of generator of such tables. Many series of analysis were performed before the implementation. These series were about observing properties of real and generated IPv6 sets of prefixes. The final application was implemented in the way that it corresponds as much as possible to real sets. The correctness of the generator was tested by comparing the bit values of generated and real IPv6 sets.
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Creating Timetables Using Genetic Algorithms
Horký, Aleš ; Matoušek, Jiří (referee) ; Minařík, Miloš (advisor)
This bachelor thesis contains design and implementation of two-phase genetic algorithm intended for creating timetable schedules at primary schools. The algorithm is designed for maximum reduction of state space of solved problem without decrease of its universality. The implementated program in C++ language is applicable for creating timetable schedules at small and medium sized schools.
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Visualization of Longest Prefix Match Algorithms
Fomiczew, Jiří ; Matoušek, Jiří (referee) ; Kováčik, Michal (advisor)
This thesis describes the design and implementation of program for vizualization of algorithms for longest pre fix match (LPM), which is one of the most important tasks for packet classi cation and routing in TCP/IP networks. It describes necessary theory and details about selected algorithms - Trie, Tree Bitmap and CPE. Furthermore, it describes the design and implementation of program for vizualization of the search process of these algorithms with emphasis on the potential use for educational purposes. Finally, it describes the possibilities for future development and expansion of the program.
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Hardware Implementation of CRC for High Speed Networks
Belešová, Michaela ; Martínek, Tomáš (referee) ; Matoušek, Jiří (advisor)
This bachelor's thesis deals with a problem of hardware implementation of CRC for high speed networks. In the first section, there is a description of basic information about CRC and several methods for CRC calculation. From methods described in the first section methods representing Galois fields and methods describing connection of units computing CRC in parallel and in series were chosen. Based on these methods an implementation was created. This implementation expects 256b input words and achieves throughput over 40Gbps. This implementation also deals with a problem of unaligned starts and ends of frames and possible occurrence of pieces from two different frames in the same word. The whole solution was designed with minimal resource usage in mind.
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IPv6 Prefix Generator
Obrusník, Vojtěch ; Kučera, Jan (referee) ; Matoušek, Jiří (advisor)
Incoming deployment of IPv6 technology in larger scale requires existence of effective route lookup algorithms suitable of manipulation with long IPv6 prefixes. Development of such algorithms is dependent on an huge amount of test data sets, which do not exist at the moment. This paper is focused on design and implementation of a tool, that would be able to generate such test data sets. Study phase of IPv6 address allocation polices and analysis of currently available pieces of prefix sets took place before the implementation. Validation of results was performed by bit value and prefix length scatter measurement.
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Mapping of Match Tables from P4 Language to FPGA Technology
Kekely, Michal ; Matoušek, Jiří (referee) ; Kořenek, Jan (advisor)
This thesis deals with design and implementation of mapping of match action tables from P4 language to FPGA technology. Goal of the thesis was to describe key principles, which need to be understood in order to design such a mapping and function of algorithms needed, apply these principles by implementing them and analyze the speed and memory requirements of such an implementation. Outcome provides configurable hardware unit capable of classifying packets and connection between the unit and match action tables from P4 language. The implementation is based on DCFL algorithm and requires less memory compared to HiCuts and HyperCuts algorithms while being comparably fast at worst-case scenarios.
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