National Repository of Grey Literature 4 records found  Search took 0.00 seconds. 
Adaptive embedded data splitter
Kazelle, Kamil ; Tošovský, Petr (referee) ; Kubíček, Michal (advisor)
This diploma work aims to invent an algorithm for use of serial interface SGMII (serial gigabit multimedia independent interface) in adaptive embedded data splitter for Gigabit Ethernet standard 1000Base-T interface and also to aplicate these algorithms to FPGA circuit.
Class D stereo audio power amplifier
Kazelle, Kamil ; Dostál, Tomáš (referee) ; Brančík, Lubomír (advisor)
The content of this project is design of stereo audio amlifier working in class D with output power 2x20W. Project includes also a design of preamplifier and power supply. This project is divided into the four parts. In first part the theory and problems of amplifiers working in class D is resumed, in the second the designed circuits are dicussed, in the third the results of simulations in the program PSpice are presented and the last part of project describes the realization and presents the results of measurements.
Class D stereo audio power amplifier
Kazelle, Kamil ; Dostál, Tomáš (referee) ; Brančík, Lubomír (advisor)
The content of this project is design of stereo audio amlifier working in class D with output power 2x20W. Project includes also a design of preamplifier and power supply. This project is divided into the four parts. In first part the theory and problems of amplifiers working in class D is resumed, in the second the designed circuits are dicussed, in the third the results of simulations in the program PSpice are presented and the last part of project describes the realization and presents the results of measurements.
Adaptive embedded data splitter
Kazelle, Kamil ; Tošovský, Petr (referee) ; Kubíček, Michal (advisor)
This diploma work aims to invent an algorithm for use of serial interface SGMII (serial gigabit multimedia independent interface) in adaptive embedded data splitter for Gigabit Ethernet standard 1000Base-T interface and also to aplicate these algorithms to FPGA circuit.

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