National Repository of Grey Literature 2 records found  Search took 0.01 seconds. 
Application of SAT Solvers in Circuit Optimization Problem
Minařík, Vojtěch ; Mrázek, Vojtěch (referee) ; Vašíček, Zdeněk (advisor)
This thesis is focused on the task of application of SAT problem and it's modifications in area of evolution logic circuit development. This task is supposed to increase speed of evaluating candidate circuits by fitness function in cases where simulation usage fails. Usage of SAT and #SAT problems make evolution of complex circuits with high input number significantly faster. Implemented solution is based on #SAT problem. Two applications were implemented. They differ by the approach to checking outputs of circuit for wrong values. Time complexity of implemented algorithm depends on logical complexity of circuit, because it uses logical formulas and it's satisfiability to evaluate logic circuits.
Polygonal Mesh Segmentation
Minařík, Vojtěch ; Havel, Jiří (referee) ; Španěl, Michal (advisor)
Bachelor's thesis deals with 3D model segmentation into particular meaningful segments. Method is based on algorithm described in article Protrusion-oriented 3D mesh segmentation The realized solution is based on assumption, that 3D models consist of a core and core attached protrusions. The segmentation algorithm consists of three main steps: core approximation, selection of salient points which indicate end of protrusion and assignment of points to appropriate segments. Implementation uses library CGAL which is useful for loading and manipulating 3D meshes.

See also: similar author names
1 Minařík, Vladimír
1 Minárik, Vladimír
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